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High Performance Multi-Channel High-Speed I/O Circuits

Ramesh Harjani, Taehyoun Oh

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ca. 96,29 €
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Springer New York img Link Publisher

Naturwissenschaften, Medizin, Informatik, Technik / Elektronik, Elektrotechnik, Nachrichtentechnik

Beschreibung

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

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Schlagwörter

High-Speed Chip-to-Chip Communications, Wireless Communication, Multi-Channel High-Speed I/O Circuits, Channel Inter-Symbol Interference, Crosstalk Cancellation and Signal Reutilization, Crosstalk Channel Modeling, Analog Circuits and Signal Processing